Developing Next-gen HPC Architectures - A Hardware Prototyping Workshop

Category
Events
Date
2016-06-23 14:00 - 18:00
Venue
Marriott Hotel, Frankfurt / Main - Hamburger Allee 2
60486 Frankfurt am Main, Deutschland

The evolution curve of the computational power of supercomputers is getting flat and after hitting the frequency wall, we are facing a critical point for Moore’s law. For these reasons experimenting with novel architectures is a must. While the trend towards heterogeneous computing in the form of coprocessors, accelerators or on-chip helper cores is more evolutionary, revolutionary approaches like neuromorphic computing are in the limelight, as well. Their common goal is to increase performance while being energy efficienct. And they all strikingly demonstrate the drive for innovation in HPC – that needs to be demonstrated and proven with prototypes.

We will cover a wide spectrum of architectural concepts, using various technologies, and addressing the requirements of user communities, either with general-purpose or domain specific approaches.

The workshop will be held in conjunction with ISC'16. A mix of invited talks and open discussion will deal in-depth with the conferences' focus topic on Exascale Architectures: Revolution vs. Evolution.

 

Preliminary Agenda

 

2:00-2:05pm Welcome Dr Estela Suarez, JSC

 

 

2:05-2:50pm

Keynote

Prof. Toshihiro Hanawa, Tokyo University

TCA and AC-CREST project 

 


Session 1: Latest ARM developments in HPC

 

2:50-3:15pm Mont-Blanc Project Dr. Filippo Mantovani, BSC

The embedded and mobile market evolves at incredible speeds. This allows for rapid development of IP blocks and several System-on-a-Chip (SoC) configurations, thus giving way for balancing performance, energy- and cost-efficiency. In the first phase of the Mont-Blanc project we advocate for HPC systems to be built from such commodity SoC currently used in the embedded and mobile market. As a first demonstrator of such an approach, the Mont-Blanc prototype will be presented: the first HPC system made-up entirely of commodity SoCs, memories, and NICs from the embedded and mobile domain. The prototype is complemented by off-the-shelf HPC networking, storage, cooling and integration solutions.

 

3:15-3:40pm SpiNNaker Project Prof. Steve Furber, University of Manchester The human brain remains as one of the enigmas of science - how does this organ upon which we all so critically depend store, process and communicate information? If we could understand more about how the brain works, what might this tell us about better ways to build computers? The SpiNNaker - Spiking Neural Network architecture - project has been 18 years in conception and ten years in construction, but is now offering a 500,000-core machine under the auspices of the EU Flagship Human Brain Project for large-scale real-time brain modelling with the goal of contributing to the global scientific quest to understand the inner workings of the brain.


Session 2: Innovative Prototyping based on Xeon Phi

 

3:40-4:05pm DEEP & DEEP-ER Projects Prof. Norbert Eicker, JSC  


Coffee break


Session 2 - continued

 

4:35-5:00pm QPACE II Project Prof. Tilo Wettig, Universität Regensburg

Numerical simulations of the fundamental theory of elementary particle physics (i.e., Lattice QCD) have been at the forefront of HPC for three decades. Dedicated supercomputers were developed in a number of projects in the US, Europe, and Japan.  I will describe the latest German project, QPACE 2, which uses Intel Xeon Phi (KNC) processors. Efficient use of these many-core processors required both algorithmic modifications (to minimize data movement) and nontrivial changes to the codes (data layout, vectorization, etc.), which I will briefly review. I will also give an outlook to QPACE 3, which will use the KNL processor.

 


Session 3: Hardware Prototyping for Exascale - What's up next?

 

5:00-5:55pm Panel Discussion Moderator: Dr. Estela Suarez, JSC

 

 

5:55-6:00pm Conclusion & Farewell Dr. Estela Suarez, JSC

 

 

 

Speakers

 

Keynote: Prof Toshihiro Hanawa, Tokyo University

Toshihiro Hanawa received the M.E. degree and the Ph.D. degree in computer science from Keio University in 1995 and 1998. He was an assistant professor of Tokyo University of Technology, Japan, from 1998 to 2007, a research fellow of Center for Computational Sciences (CCS), University of Tsukuba, from 2007 to 2008, an associate professor of CCS, from 2008 to 2013, and a project associate professor of Information Technology Center, The University of Tokyo, from 2013 to 2015. Since Dec. 2015, he is an associate professor of Information Technology Center, The University of Tokyo. He belongs to “Research and Development on Unified Environment of Accelerated Computing and Interconnection for Post-Petascale Era,” a project supported by JST/CREST, Japan, from 2012 to 2018. His research interests include computer architecture, interconnection network. Dr. Hanawa is a member of IEEE CS and IPSJ.

 

Mont-Blanc Project: Dr Filippo Mantovani

Filippo Mantovani is senior researcher at the Barcelona Supercomputing Center (BSC). He graduated in mathematics and holds a PhD in Computer Science from University of Ferrara, Italy. He has been a scientific associate at the DESY laboratory in Zeuthen, Germany, and at the University of Regensburg, Germany. He spent most of his scientific career in computational physics, computer architecture and high-performance computing, contributing to the Janus, QPACE and QPACE2 projects. He joined BSC’s Mont-Blanc project in 2013, becoming the technical coordinator of the project shortly after.

 

SpiNNaker Project: Prof Dr Steve Furber

Steve Furber CBE FRS FREng is ICL Professor of Computer Engineering in the School of Computer Science at the University of Manchester, UK. After completing a BA in mathematics and a PhD in aerodynamics at the University of Cambridge, UK, he spent the 1980s at Acorn Computers, where he was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor. Over 75 billion variants of the ARM processor have since been manufactured, powering much of the world's mobile and embedded computing. He moved to the ICL Chair at Manchester in 1990 where he leads research into asynchronous and low-power systems and, more recently, neural systems engineering, where the SpiNNaker project is delivering a computer incorporating a million ARM processors optimised for brain modelling applications.

 

DEEP/-ER Project: Prof Dr Norbert Eicker

Norbert Eicker is Professor for Parallel Hardware and Software Systems at Bergische Universität Wuppertal and head of the research group Cluster Computing at Jülich Supercomputing Centre. Before joining JSC in 2004, Norbert was with ParTec from 2001 on working on the Cluster Middleware ParaStation. During his career he was involved in several research and development projects including the ALiCE-cluster in Wuppertal, JULI and JSC's general purpose supercomputer JuRoPA. Currently he is acting as the chief architect for the DEEP and DEEP-ER projects. Norbert holds a PhD in Theoretical Particle Physics from Wuppertal University.

 

QPACE II Project: Prof Dr Tilo Wettig

Tilo Wettig is a professor in the Department of Physics at the University of Regensburg. He is the Principal Investigator of the QPACE and iDataCool projects. Prior to this he played a leading role in the development of the QCDOC supercomputer, which served as a prototype for IBM's BlueGene/L. His research interests include Lattice Quantum Chromodynamics, efficient algorithms for massively parallel architectures, and the development of energy-efficient supercomputers.  He has published over 120 scientific articles.

 

Workshop Organizers

 

Dr. Estela Suarez, Project Manager DEEP & DEEP-ER, Jülich Supercomputing Centre

Dr. Filippo Mantovani, Technical Coordinator Mont-Blanc Project, Barcelona Supercomputing Centre

 

 

 
 

All Dates

  • 2016-06-23 14:00 - 18:00

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