Term Definition

To evaluate the DEEP-ER concept and to prove its programmability, 7 real-world HPC applications are ported to the DEEP-ER system. They serve to test the system, to compare its performance with respect to standard architectures, but obviously also to propose improvements to the system's hardware and software. They form an integral part in the DEEP and DEEP-ER Co-Design efforts.


Application Specific Integrated Circuit, Integrated circuit customised for a particular use.


Global File system developed by the Fraunhofer Institute ITWM, a high-performance parallel I/O system to be adapted to the extended DEEP architecture and optimised for the DEEP-ER prototype. It was formerly known as FhGFS. For more information please visit:


In the DEEP and DEEP-ER projects we follow an approach we call "true" Co-Design. It reaches from hardware to middleware/systemware to tools to applications. Only via this all-encompassing ‘true’ Co-Design it is possible to achieve Exascale performance on an application level.


Dynamical Exascale Entry Platform, in short DEEP, is a collaborative European Commission (EC) funded research project in the High Performance Computing (HPC) area. It is the pre-decessor project of DEEP-ER.

More information on the DEEP project website:

Dynamical Exascale Entry Platform - Extended Reach, in short DEEP-ER, is a collaborative European Commission (EC) funded research project in the High Performance Computing area.

Exascale10 I/O software, which forms part of the DEEP-ER I/O stack. It mainly provides new collective I/O methods and extensions.


EC = European Commission, the DEEP-ER funding authority.

Official EC website:


EEP stands for European Exascale Projects. To date it is a lose cooperation of the first Exascale projects funded under the European Commission's Seventh Framework Programme.

More on the collaborating projects:


An Exaflop are 1018 Floating point operations per second.


Computer systems or applications, which are able to run with a performance above 1018 Floating point operations per second. The aim of the DEEP-ER project is to develop an exascale-able prototype system. 


High speed interconnect technology for cluster computers developed by Heidelberg University. Product specific informatin is available here.


Field-Programmable Gate Array, Integrated circuit to be configured by the customer or designer after manufacturing


The HMC, short for hybrid memory cube, forms part of the NAM prototype in DEEP-ER. The second component to the NAM prototype is the NAM controller.

In DEEP-ER, project partner University of Heidelberg experiments with HMC in the open source project openHMC.

More on openHMC:


High Performance Computing