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The DEEP-EST prototype will come together during the course of 2019. This is the result of strict and detailed co-design process with six application teams. It will include three modules:

 

 

  • Cluster Module (CM): Intel(r) Xeon(r) based HPC Cluster with high single-thread performance and a universal Infiniband interconnect.

  • Data Analytics Module (DAM): Intel (r) Xeon(r) based Cluster with non-volatile, byte-addressable memory, one Intel Stratix 10 FPGA and one NVIDIA Tesla V100 card. Nodes will be interconnected by 40 Gb/s Ethernet and a 100 Gb/s EXTOLL fabric.

  • Extreme Scale Booster (ESB): NVIDIA Tesal-base nodes with a small Intel(r) Xeon() CPU and EXTOLL 3D Torus interconnect; objective is to run all applications from the local V100 memeory, and use GPUDirect technology to bypass CPU for network communication.
    The CM will have 50 nodes, and the ESB is planned for 75 nodes - both will use Megware's ColdCon liquid cooling technology. The DAM will have 16 air-cooled nodes with a large memory buildout.


  • A storage and service module will provide high-performance disk storage and  login nodes. This module will use 40 Gb/s Ethernet, and run the BeeGFS parallel file system.

A network federation infrastructure ties all the modules together, supporting MPI and IP communication. It is implemented using fabric-to-fabric gateways, and for MPI utilizes high-bandwidth RDMA communication.

In addition, Network Attached Memory nodes will provide persistent shared memory resources at EXTOLL network speeds, and an experimental Global Communication Engine will drive collective MPI communication on the ESB, with major projected improvements compared to conventional implementations.

Thus, the DEEP-EST prototype demonstrates the benefits of the Modular Supercomputing Architecture: parts of complex applications or worklflows can run on the best matching architecture -- CM for codes with limited parallelism relying on per-thread performance, ESB for highly scalable codes, and the DAM for machine laerning and data analytics codes that require huge memory, high I/O performance an dcan benefit from GPGPU or FPGA accelerators. 
 
One overriding objective in the DEEP-EST co-design process was the minimization of energy used -- selection of leading-edge processors and accelerators, careful matching of compentents to achive highest end-to-end performance, and provision of real-time energy monitoring data are key elements here. One noteworthy result is that we will be able to measure the total node energy consumption for each CM and ESB nodes in realtime, including CPU, memory, accelerators and NICs. This will enable higher-level software layers to reach the right decisions in minimizing energy use. 

Hardware